1. Field of the Invention
The present invention relates to a slit recess channel gate, and more particularly, to a slit recess channel gate having a tapered gate conductor.
2. Description of the Prior Art
With continuing shrinkage of device feature size, the so-called short channel effect (SCE) due to shrunk gate channel length has been found hindering the integrity of integrated circuit chips. Many efforts have been made for solving this problem, for example, by reducing the thickness of the gate oxide dielectric or by increasing the doping concentration of source/drain. However, these approaches adversely affect the device reliability and speed of data transfer on the other hand, and are thus impractical.
A newly developed recessed-gate MOS transistor becomes most promising. In the filed of Dynamic Random Access Memory (DRAM), the recessed-gate technology may be used to improve the integrity of the memory chip. Typically, the recess-gate MOS transistor has a gate insulation layer formed on sidewalls and bottom surface of a recess etched into a substrate, a conductive filling the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate.
However, some problems have been met when constructing the recess-gate MOS transistor. For example, in order to form the recess gate MOS transistor, a first lithographic and etching process is first performed to etch a gate trench into the semiconductor substrate. After filling the gate trench with a gate material layer, a second lithographic and etching process is performed to define a gate conductor (GC) on the recess gate. The misalignment between the GC and the recess gate of the recess-gate MOS transistor device is easy to occur, thereby affecting the yield of the devices.